Because timers consume more stack space

Because hardware interrupts are more important than software interrupt requests

Because human-perceived latency is critical

Because timers already handle interruptions and must never be interrupted

It eliminates the need for decoding logic

It enables limited parallelism while avoiding the size overhead of full horizontal encoding

It guarantees fastest possible execution

It allows unlimited signal activation per cycle

Use DIV AB with B=16 because division and multiplication are symmetric

Use RRC A four times because rotating right by four positions equals times 16

Execute four consecutive left shifts (e.g., using RL A four times) to multiply by 2 four times

Execute one left shift and one SWAP to achieve times 16

It selects which interrupt has highest priority among the different interrupt service requests

It acts as a master gate that must be enabled for any interrupt to occur

It automatically enables all interrupts on reset

It replaces individual enable bits

0x9F

0x90

0x9A

0x0A

A=0x01C2 and B unchanged

A=0x01 and B=0xC2

A=0xC2 and B=0x01

A=0xC2 and B=0x18

The most recently asserted request

The first active request encountered along the priority chain

All active requests simultaneously

The highest-numbered active request