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BCE 121 COMPUTER ORGANIZATION AND ARCHITECTURE MAY TO AUGUST 2025 SEMESTER BLENDED 2.0 UNIT
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8C3. During DMA transfer, the CPU:
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7C3. DMA stands for:
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9C3. Which device uses block-level access?
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6C3. Interrupt-driven I/O improves performance by:
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50C3. Which device uses inkjet technology?
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5C3. In polled I/O, the processor:
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49C3. The role of a memory controller is to:
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4C3. Handshaking in I/O communication ensures:
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45C3. What helps prioritize multiple interrupts?
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46C3. The refresh operation in DRAM is necessary because:
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