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IN1006 Systems Architecture (PRD1 A 2024/25)

IN1006 Systems Architecture (PRD1 A 2024/25)

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Suppose we have a byte-addressable computer using direct mapping with 16-bit main memory addresses and 32 blocks of cache. If each block contains 8 bytes, determine the size of the offset field.

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Suppose we have a byte-addressable computer using direct mapping with 16-bit main memory addresses and 32 blocks of cache. If each block contains 8 bytes, determine the size of the block field.

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Which of the below is the best description of term ‘superscalar’?

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A processor that executes more than one instruction during a clock cycle.

A processor that executes more than one instruction during a clock cycle by using clock doubling.

A processor that executes more than one instruction during a clock cycle by using multiple execution units.

A processor that executes more than one instruction during a clock cycle by using pipelining.

A processor that executes more than one instruction during a clock cycle by using multiple processor cores.

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Which is the correct ordering of the stages of the MIPS pipeline?

Fetch instruction, execute, decode/read register, access memory, write to register.

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Fetch instruction, decode/read register, execute, access memory, write to register.

Fetch instruction, decode/read register, access memory, execute, write to register.

Fetch instruction, decode/read register, execute, write to register, access memory.

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Which of the following is the best explaination of why DRAM is slower than SRAM.

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DRAM uses a capacitor.

The question above is constructed wrongly: DRAM is faster than SRAM

SRAM uses floating-gate transistors, whereas DRAM does not.

SRAM supports wider buses than DRAM.

DRAM is cheaper, therefore slower.

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Which of the following is the correct ordering of the following memory types in decreasing order of cost per unit memory.

Network storage, hard disk drive, flash memory, DRAM, SRAM.

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Network storage, hard disk drive, flash memory, SRAM, DRAM.

flash memory, SRAM, DRAM, hard disk drive, network storage.

SRAM, DRAM, flash memory, hard disk drive, network storage.

SRAM, flash memory, DRAM, hard disk drive, network storage.

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What is the maximum number of instructions that can be executed simultaneously for the MIPS pseudo-code below?

add a, b, c
add d, b ,c
add g, e ,d
add h, e, f
add f, a, b

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Which of the following is the best description of ILP?

Instruction Level Parallelism (ILP) is a measure of how many of the operations in a computer program can be performed simultaneously. See: http://en.wikipedia.org/wiki/Instruction_level_parallelism

It is a measure of how many number of superscalar execution units there are in a CPU.

It is a measure of how many of the operations in a computer program use the same registers.

It is a measure of how much of a pipeline is utilised by a computer program.

It is a measure of how many of the operations in a computer program can be performed simultaneously.

It is a measure of how many of the registers in a computer program are used.

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Match the correct term to the description

Percentage of time it is not

Data is locally available => no penalty to access

Data is on a lower level => penalty from 1-30 cycles to access

Time required to access data at a given memory level

the time required to process a miss, including the time that it takes to replace a block of memory plus the time it takes to deliver the data to the processor

Percentage of time data is found at a given memory level

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Choose the correct answers that show different

applications where ROMs (Read-Only Memory) are often used.

Are used extensively in calculators and peripheral devices

such as laser printers, which use this memory to store their fonts.

Only in old computers and some analog television (TV).

All of the other answers.

Many appliances, toys, and most automobiles use this type of memory to maintain

information when the power is shut off.

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