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CA & OS (Computer Architecture) - EFREI - Fall 2026

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Risque structurel

Un  aléa structurel survient lorsque deux instructions ou plus, se trouvant à des phases d'exécution différentes, demandent l'accès à la même ressource matérielle (mémoire, unité d'exécution, etc.). En MIPS, ce problème est facilement observable lors de l'utilisation de l'unité de division en virgule flottante. Le programme ci-dessous illustre cette situation.

    .data

A:    .word 3

v:    .double

0.0

x:    .double 10.0

y:    .double

5.0

z:    .double 0.0

    

 

  .text

main:        

       LDC1 f2,x(r0)      ;f2=x (ld.d f2,x(r0) )

    LDC1 f3,y(r0)      ;f3=y (ld.d f3,y(r0) )

    

    div.d

f5,f3,f2    ;f5=x/y

    div.d f6,f2,f3  

 ;f6=y/x

    add.d f8,f5,f6  

 ;f8=(x/y)+(y/x)

    

    add.d

f4,f3,f3

    mul.d f7,f13,f2

    mul.d

f13,f2,f4

    mul.d f9,f4,f13

 

  

    SDC1 f8,z(r0)

    SDC1 f9,v(r0)

    syscall 0

Analysez ce programme et calculez manuellement le nombre de cycles d'horloge nécessaires à son exécution sur un processeur séquentiel. 

Supposons que l'exécution de chaque instruction prenne 5 cycles d'horloge,

que l' instruction div.d prenne 23 cycles d'horloge supplémentaires,

mul.d 6 cycles d'horloge supplémentaires et add.d 3 cycles d'horloge supplémentaires .

Combien de cycles d'horloge sont nécessaires pour exécuter ce programme sur un processeur séquentiel ?

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Expliquez brièvement pourquoi l'instruction donnée en réponse à la question précédente engendre un risque structurel.

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Nombre de cycles de décrochage structurel (STR)

Analysez le diagramme du cycle d'horloge et comptez manuellement le nombre de cycles de blocage structurel (STR).

(Ce comptage doit être effectué manuellement car les blocages structurels ne sont pas correctement comptabilisés dans la fenêtre statistique de WinMIPS64).

Quel est le nombre de cycles de décrochage structurel (STR) ?

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Analysez le diagramme du cycle d'horloge et trouvez l'instruction qui provoque un blocage structurel (StDiv).

Inscrivez cette instruction dans la case réponse.

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Observation of the pipelined execution of a simple program

In this section you will try to evaluate the impact of the pipelined execution of the program on its performance.

Prepare and load the test program (copy & paste following code):

      .data

A:    .word 10

B:    .word 8

C:    .word 0

    

      .text

main:    ld r4,A(r0)

         ld r5,B(r0)

         dadd r3,r4,r5

         sd r3,C(r0)

         syscall 0

In Settings go to “Simulation” tab then  check and enable the option “CPU forwarding”.

Execute the program in single cycle instruction mode. Observe the pipeline window and the clock cycle diagram.

What is the number of clock cycles (n) used for the execution of  this program that appears in the "Statistic" window.

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Extending the program

Insert another 9 dadd r3,r4,r5 instructions just after first dadd instruction of the sample program. 

After this you should have a total 10 dadd r3,r4,r5 instructions in your program. 

Execute modified program.

Write down into the box below the nMOD value which is the number of the clock cycles used for the execution of modified program. Be sure that forwarding mechanism is active (Configure->Enable forwarding option is active)

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Calculating speedup value

 speedup=nsequential/n

n value should be taken form Question 7.

nsequential value should be taken form Question 8

Put the calculated value into the answer box. 

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In this section, you will evaluate how long it takes to execute different types of the instructions of the MIPS computer.

Number of clock cycles for dadd instruction (integer addition)

Load and execute in step mode following program:

        .text

main:    dadd

r1,r0,r1 ; r1 = r0+r1 

         nop

         syscall 0

As a result of the execution you should receive clock cycle diagram of the execution similar to this on the image:

Clock cycle diagam of execution of dadd instruction.

Analyze this clock cycle diagram of execution of the program and answer the question: 

How many clock cycles does the execution of the instruction dadd r1,r0,r1 take (each box in clock cycle diagram represents one clock tick )?

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Number of clock cycles for add.d instruction (floating point addition).

Load and execute in step mode following program:

        .text

main:    add.d

f1,f0,f1

         syscall 0

Analyze clock cycle diagram of execution of the program and answer the question:

How many clock cycles does the execution of the instruction add.d f1,f0,f1 take ?

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How many clock cycles does the execution of the instruction syscall 0 take?

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