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CA & OS (Computer Architecture) - EFREI - Fall 2026
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Control hazard
Control hazards are mainly related to the processor's execution of jump instructions (unconditional or conditional). To observe the behavior of the pipeline during the execution of jump instructions, the following program will be used:
;WinMIPS64 control hazard; just simple for loop in MIPS asm .datan: .word 3res: .word 0 .textmain: xor r16,r16,r16 ; r16 = 0 loop counter xor r2,r2,r2 ; r2 = 0 lw r17, n(r0) ; number of loop executions nop ; must be here to avoid RAW with next instr. start_loop: dsub r9, r16, r17 ; $t1= r9 nop ; must be here to avoid RAW with next instr. beqz r9, end_loop # code block daddi r2,r2,2 dsub r2,r2,r0 ; r0 always contains 0 daddi r16,r16,1 ; loop counter increment j start_loopend_loop: sw r2,res(r0) halt
Find the part of the clock cycle diagram that shows the first execution of the beqz r9, end_loop instruction. Analyze it and answer the questions.
Which instruction is fetched next (enters in the IF phase on clock cycle diagram) ?
Quelle instruction est exécutée ensuite beqz r9, end_loop(entrée dans la phase EX sur le diagramme du cycle d'horloge) ?
Trouvez la partie du diagramme du cycle d'horloge qui illustre la dernière exécution de l' j start_loopinstruction. Analysez-la et répondez aux questions suivantes.
Quelle instruction est récupérée ensuite ?
Quelle instruction est exécutée ensuite beqz r9, end_loop(entrée dans la phase EX sur le diagramme du cycle d'horloge) ?
L'exécution de l'instruction indiquée dans la réponse à la question précédente est-elle en cours ?
Si l'exécution de l'instruction est suspendue (la réponse à la question précédente était VRAIE ), comment expliquer cette suspension ?
L'exécution de l'instruction indiquée dans la réponse à la question précédente est-elle en cours ?
Si l'exécution de l'instruction est suspendue (la réponse à la question précédente était VRAIE), comment expliquer cette suspension ?
Analyze the program and try to evaluate the value of the res if the execution of the instruction that causes WAR stall was proceeded without waiting for the execution of the previous instruction to complete.
Calculated “wrong” res value:
W-A-R hazard
This type of hazard may occur when the latter instruction (j) stores the result of its execution in the resource (register or memory location) that earlier instruction (i) uses as their argument. The problem appears when the execution of earlier instruction (i) is delayed, and the latter instruction (j) is finished before earlier instruction (i) can take its argument. It may lead to a wrong result of the execution instruction (i). The typical way to remove such a dependency is to delay the completion of the execution instruction (j) until the execution of instruction (i) is completed. To illustrate this problem, the following code will be used:
;WinMIPS64 WAR hazard example .dataA: .double 10.0B: .double 5.0C: .double 3.5D: .double 1.0E: .double 3.14.0res: .double 0.0 .textmain: l.d f2,A(r0) l.d f3,B(r0) l.d f4,C(r0) l.d f5,D(r0) l.d f6,E(r0) add.d f2,f2,f3 sub.d f2,f2,f4 mul.d f4,f5,f6 s.d f2,res(r0) halt
Enable data forwarding mechanism and execute the example program. Analyze the clock cycle diagram and find the instruction that causes WAR stall.
Mark the instruction that causes WAR stall.