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SY Common ISE ODD 25-26

SY Common ISE ODD 25-26

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Partial

dependency is removed in which normal form?

2NF

3NF

1NF

4NF

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In strict Two-Phase Locking, when are all exclusive locks released?

Before commit

After read operation

Immediately after use

After transaction commit or abort

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Which anomaly occurs when a transaction updates a value already read by another transaction?

Read-Read Conflict

Write-Write Conflict

Read-Write Conflict

Write-Read Conflict

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Which of these is NOT a function of a Database Administrator?

Backup and recovery

❌

Defining security roles

❌

Query writing by all end users

✅

Performance tuning

❌

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Which of the following statement(s) is (are) true?

The cache is slower than the primary memory.

The primary memory stores the necessary instructions and information for the

processor.

The memory system is designed as a hierarchy of various levels.

The secondary memory acts as a backup.

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Which of the following best describes a composite attribute?

Derived from another attribute

❌

Takes multiple values

❌

Used for weak entities only

❌

Can be divided into subparts

✅

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Which transaction state means execution is complete but changes not yet permanent?

Committed

Failed

Partially Committed

Active

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Designer of a processor company wants total of 14 instructions in the instruction set. He experiences a total of 75 unique control signals in order to execute them. The instruction set has ADD and SUB operations in addition to data transfer and logical operations. The designer starts designing the control unit using one of the two approches of the design. As an auditor, you are supposed to analyze the design and recommend the optimum approch for the design. The appropriate suggestion would be:

Nanoprogrammed with Nanoinstuctions

Microprogrammed with Horizontal Microinstructions

A mix design of Hardwired and Microprogammed

Hardwired with Finite State Machine

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Which of the following is false concerning the processor?

The processor fetches instructions from memory for execution.

The processor communicates with the input/output device with the help of an

interface.

The processor does not use cache memory to communicate with the memory.

The processor directly communicates with the memory.

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A computer requires 39 bits to address a single word in memory. Each word in this

computer is 16 bits. What is the size of the memory?

3 TB

1 TB

2 TB

4 TB

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