A PIC16F18877 processor is configured so that it runs based on an external clock signal of 6 MHz. Presuming that the instruction pipeline is not broken, how many instruction cycles will be equivalent to a 1 millisecond delay?

Fill in the blank:

A PIC16F18877 processor is configured so that it runs based on an external clock signal of 0.4 MHz. Presuming that the instruction pipeline is not broken, an instruction will be executed every __________________.

 movf Reg,W
 btfss Reg,7
 goto Done
 sublw 0
Done movwf Reg

  Processor A:
         RISC
         8 bit address space
         8 bit instructions
         4 MHz max. clock speecd
         Averages 4 clock cycles per instruction
         Algorithm Q code size: 80 instructions
         Cost: 20 money units
 
 Processor B:
         CISC
         8 bit address space
         16 bit instructions
         20 MHz max clock speed
         Averages 10 clock cycles per instruction
         Algorithm Q code size: 40 instructions
         Cost: 300 money units

  
         loop    incfsz  var,f
                 goto    loop