What value is to be considered for a “don’t care condition”?

What must be used along with synchronous control inputs to trigger a change in the flip flop?

In Digital Circuits, which of the following options represent the synchronous control inputs in a T flip flop?

Which of the following points is not correct regarding an Ex – NOR gate in Digital Electronics?

What gate is placed between clock input and the input of AND gate to convert a positive level triggered flip – flop to a negative level triggered flip – flop?

How many AND gates are required to construct a 4 – bit parallel multiplier if four 4 – bit parallel binary adders are given?

Which of these flip – flops cannot be used to construct a serial shift register?

Which characteristic of IC in Digital Circuits represents a function of the switching time of a particular transistor?

What will be the frequency of the output from a JK flip – flop, when J = 1, K = 1, and a clock with pulse waveform is given?

When does a negative level triggered flip-flop in Digital Electronics changes its state?