Port ( S

: in STD_LOGIC_vector(1 downto 0);

                I0,

I1, I2, I3 : in STD_LOGIC;

                               q

: out STD_LOGIC);

end mux_2;

architecture ar2_mux_2 of mux_2

is

begin

with S select

q<=        I0 WHEN "00",

                               I1

WHEN "01",

                               I2

WHEN "10",

                               I3

when others;

end ar2_mux_2;

entity mux_2 is

    Port ( S

: in STD_LOGIC_vector(1 downto 0);

                I0,

I1, I2, I3 : in STD_LOGIC;

                               q

: out STD_LOGIC);

end mux_2;

architecture Behavioral of mux_2

is

begin

q<=        I0 WHEN S="00" ELSE

                                               I1

WHEN S="01" ELSE

                                               I2

WHEN S="10" ELSE

                                              I3;

end Behavioral;

    Port ( S

: in STD_LOGIC_vector(2 downto 0);

                I0,

I1, I2, I3, I4, I5, I6, I7 : in STD_LOGIC;

                               q

: out STD_LOGIC);

end mux_2;

architecture ar2_mux_2 of mux_2

is

begin

with S select

q<=        I0 WHEN "000",

                               I1

WHEN "010",

                               I2

WHEN "100",

                               I3

when "101”,

I4 when  others;

end ar2_mux_2;