Consider a benchmark where 5% of the instructions are inconditional jumps, 4% ar...
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Consider a benchmark where 5% of the instructions are inconditional jumps, 4% are calling to routines, 26% are conditional branch (the branch condition is satisfied in 78% of the cases) and 5% are load instructions (lw) (38% of the loads are followed by an instruction with data dependency).
Consider two processors P0 and P1 both using the branch not taken predition technique. The architecture of the processors uptade the PC as follow:
P0: j & jal, PC is updated in ID stage; conditional branches (beq & bne) in MEM stage
P1: j & jal, PC is uptated in IF stage*; conditional branches (beq & bne) in EX stage
The data hazards are solved by hardware (full forwarding).
Ignoring the initial transiet (4 cycles), calculate the CPI for the processor P1, (give the result with three decimal digits at least).* This configuration is possible by using a (BTB)Want instant access to all verified answers on informatica.cv.uma.es?
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