is to let the hardware issue an instruction as soon as its data dependencies are satisfied.

is to fetch and issue multiple instructions per cycle to keep the pipeline units busy.

is to let the hardware change destination register to store the result on the fly.

is to allows an instruction to read its arguments before they’ve been stored in a register. (Route the data as soon as it is calculated to an earlier pipeline stage).

is to handle a control hazard (conditional branches) by guessing next instructions to be executing.