Don't know/no answer

Hardware cannot support a combination of instructions in the same clock cycle, e.g. two simultaneous memory accesses.

Instruction depends upon the results of a previous instruction still in the pipeline, e.g. compound math expressions.

A gap in the pipeline where some or all of the stages are not processing an instruction.

Loading instructions into pipeline which try to access memory at the same stage.

Executing an instruction in the pipeline whose execution depends upon a yet unknown condition check.