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For the following truth table when the circuit is synthesized as Y=B'C+AB, the glitch might happen, when
B=1, A=1, C goes from 1 to 0
A=0, B=1, C goes from 0 to 1
A=1, C=1, B goes from 1 to 0
B=0, C=1, A goes from 1 to 0
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