A sequential logic circuit is modeled by the Verilog HDL code in Listing below. Which type of flip-flop/latch is modeled by this Verilog code?

  module gate_ff2(
  clk          ,
  rstn         ,
  in_0         ,
  in_1         ,
  q            
  );
  input         clk            ;//Input clock
  input         rstn           ;//A-sync reset signal, low active
  input         in_0           ;
  input         in_1           ;
  output        q              ;
  reg           q              ;
  wire  [ 1:0]  in             ;
  assign in = {in_0,in_1};
  always @ (posedge clk or negedge rstn) begin
    if (!rstn) begin
      q <= 1'b0;
    end
    else begin
      case (in)
      2'b00:   q <= q;  
      2'b01:   q <= 1'b0;
      2'b10:   q <= 1'b1;
      default: q <= !q;
      endcase 
    end
  end
  endmodule