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A Random Access Memory (RAM) core named IETA_UNIT has the following ports: ...
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A Random Access Memory (RAM) core named IETA_UNIT has the following ports:
PORT TYPE
|
PORT NAME
|
BITWIDTH
|
Inputs
|
CLK
|
1
|
|
RESET
|
1
|
|
G_IN
|
6
|
Outputs
|
D_OUT
|
11
|
|
TC
|
1
|
Bidirectional
|
WT
|
9
|
The entity of IETA _UNIT is given below:
entity A
Port(CLK : B;
RESET : C
G_IN : D
D_OUT : E;
TC : F;
WT : G);
end H
Letters A,B,C,D,E,F,G,H are used in place of required syntax for the entity of