Consider a MIPS processor with the configuration (1). The miss penalty is 17 cycles. Calculate the number of cycles of the memmory stage (MEM stage) when the instruction sw $3, 240($7) is executed taking into account that memory position (data) of this instruction is not found in the cache memory. We also know that there is a write buffer and it is not full.

Configurations:

(0) Write through, no-write allocate

(1) Write through, write allocate