We take again the 4-bit integrated decimal counter (0 to 9) that we experimented with in the lab and recall its inputs and outputs :

Priority inputs, all active low :

• = Counter enable control
• = Parallel load control

•     = Count up / count down selection

Data inputs and outputs :

• A,

  B, C and D  = Parallel data inputs

• Q

  _A

  ,

  Q

  _B, Q_C et Q_D  = Parallel data inputs

• A corresponds to the least significant bit

• B corresponds to the most significant bit of the counter

Determine the sequence of numbers generated in a loop by the counter when it is configured as shown in the figure below :