Задано модуль: module sequence_detector ( input clk, input ...
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Задано модуль:module sequence_detector ( input clk, input reset, input bit_in, output reg sequence_found); reg [3:0] state; always @(posedge clk or posedge reset) begin if (reset) state <= 4'b0000; else state <= {state[2:0], bit_in}; end assign sequence_found = (state == 4'b0011);endmodule Умова:
На вхід bit_in подається послідовність бітів: 0, 1, 0, 0, 1, 1, 0, 0, 1, 1.
Визначити:
Номери тактів (через кому), при яких sequence_found == 1
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