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Control hazard Control hazards are mainly related to the processor's execution...
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Control hazard
Control hazards are mainly related to the processor's execution of jump instructions (unconditional or conditional). To observe the behavior of the pipeline during the execution of jump instructions, the following program will be used:
;WinMIPS64 control hazard; just simple for loop in MIPS asm .datan: .word 3res: .word 0 .textmain: xor r16,r16,r16 ; r16 = 0 loop counter xor r2,r2,r2 ; r2 = 0 lw r17, n(r0) ; number of loop executions nop ; must be here to avoid RAW with next instr. start_loop: dsub r9, r16, r17 ; $t1= r9 nop ; must be here to avoid RAW with next instr. beq r9, r0, end_loop ; branch if equal -> if (r9 == (r0=0)) go to end_loop # code block daddi r2,r2,2 dsub r2,r2,r0 ; r0 always contains 0 daddi r16,r16,1 ; loop counter increment j start_loopend_loop: sw r2,res(r0) syscall 0
Find the part of the clock cycle diagram that shows the first execution of the beqz r9, end_loop instruction. Analyze it and answer the questions.
Which instruction is fetched next (enters in the IF phase on clock cycle diagram) ?