entity pelda_12_generate_es_vagy_kapu_b is

GENERIC ( N : natural :=4);

    Port (A: in STD_LOGIC_VECTOR(N-1

downto 0);

          B: in STD_LOGIC_VECTOR(N-1

downto 0);

          C:  STD_LOGIC_VECTOR(N-1 downto 0);

           q : out

STD_LOGIC_VECTOR(N-1 downto 0));

end pelda_12_generate_es_vagy_kapu_b;

architecture Behavioral  of

pelda_12_generate_es_vagy_kapu_b is

signal s:  STD_LOGIC_VECTOR(N-1

downto 0);

begin

G1: FOR i IN A'RANGE GENERATE

                s(i)<=A(i) and

B(i);

                q(i)<=s(i) and

C(i);

END GENERATE;

end Behavioral;

entity

pelda_12_generate_es_vagy_kapu_b is

GENERIC ( N :

natural :=4);

    Port (A: in STD_LOGIC_VECTOR(N-1 downto 0);

          B: in STD_LOGIC_VECTOR(N-1 downto 0);

          C: 

STD_LOGIC_VECTOR(N-1 downto 0);

           q : out STD_LOGIC_VECTOR(N-1 downto

0));

end

pelda_12_generate_es_vagy_kapu_b;

architecture

Behavioral  of

pelda_12_generate_es_vagy_kapu_b is

signal s:  STD_LOGIC_VECTOR(N-1 downto 0);

begin

G1: FOR i IN

A'RANGE GENERATE

                s(i)<=A(i) or B(i);

                q(i)<=s(i) and C(i);

END GENERATE;

end Behavioral;

entity pelda_12_generate_es_vagy_kapu_b is

GENERIC ( N : natural :=4);

    Port (A: in STD_LOGIC_VECTOR(N-1

downto 0);

          B: in STD_LOGIC_VECTOR(N-1

downto 0);

          C:  STD_LOGIC_VECTOR(N-1 downto 0);

           q : out

STD_LOGIC_VECTOR(N-1 downto 0));

end pelda_12_generate_es_vagy_kapu_b;

architecture Behavioral  of

pelda_12_generate_es_vagy_kapu_b is

signal s:  STD_LOGIC_VECTOR(N-1

downto 0);

begin

G1: FOR i IN A'RANGE GENERATE

                s(i)<=A(i) or B(i);

                q(i)<=s(i) or C(i);

END GENERATE;

end Behavioral;

entity pelda_12_generate_es_vagy_kapu_b is

GENERIC ( N : natural :=4);

    Port (A: in STD_LOGIC_VECTOR(N-1

downto 0);

          B: in STD_LOGIC_VECTOR(N-1

downto 0);

          C:  STD_LOGIC_VECTOR(N-1 downto 0);

           q : out

STD_LOGIC_VECTOR(N-1 downto 0));

end pelda_12_generate_es_vagy_kapu_b;

architecture Behavioral  of

pelda_12_generate_es_vagy_kapu_b is

signal s:  STD_LOGIC_VECTOR(N-1

downto 0);

begin

G1: FOR i IN A'RANGE GENERATE

                s(i)<=A(i) and

B(i);

                q(i)<=s(i) or C(i);

END GENERATE;