Consider a RISC-V architecture of 6 states IF, ID, EX1,EX2,M,WB where the new stage EX2 is due to the multiplication operation (mul). This operation takes two cycles. Thus, the adition/substraction/logical operations take one cycle (and calculate the result in the EX1 stage) whereas de multiplication calculate its result in EX2.

Calculate the execution time (in ns.) for the next code, assuming that the processor has a hazard unit to insert as many bubbles (stalls) as required and there are forwarding in the RF (Register File) only (no bypasses in the rest of stages). The cycle time is 19 ns.

or   $25, $14,$19