Consider a MIPS processor with a main meory of 16 Mbytes, with a cache of 4 Kbyt...
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Consider a MIPS processor with a main meory of 16 Mbytes, with a cache of 4 Kbytes, with write-back policy, direct mapped and blocks of 64 words. The miss penalty is 27 cycles. Nevertheless, if a block has to be copied from Cache to Main Mermory, the miss penatly is doubled. Calculate the number of cycles of the memmory stage (MEM stage) when the instruction lw $5, 120($15) is executed taking into account that this instruction accesses to Main Memory address 0x75B53C to get the data. In the nex table you have some information about the control area of the data cache (the valid bit of the cache blocks in the table is 1; in the rest of blocks the valid bit is 0).
Block=num. of block of Cache, D=Dirty bit
| Block | D | TAG |
|---|---|---|
| 0xA | 0 | 75B |
| 0x5 | 0 | 55B |
| 0xD | 1 | CF8 |