It involves designing a 4-bit serial-parallel load register with the following inputs and outputs :

• L

  = Parallel load control, active low (

  L=1 : parallel load; L=0 serial load and shift right)

• E

  _S

  = Serial data input

• I

  ₀

  ,

  I

  ₁, I₂ et I₃  = Parallel data inputs
• Q0 corresponds to the leftmost flip-flope
• Q3 corresponds to the rightmost flip-flope

The combinational circuit synthesizing the input D_K of the k^th 

flip-flop then follows the following logical

expressions