Crowdly
Додати до Chrome
UEF 1.2.1:Architectures évoluées des ordinateurs
Шукаєте відповіді та рішення тестів для UEF 1.2.1:Architectures évoluées des ordinateurs? Перегляньте нашу велику колекцію перевірених відповідей для UEF 1.2.1:Architectures évoluées des ordinateurs в esiclass.esi.dz.
Отримайте миттєвий доступ до точних відповідей та детальних пояснень для питань вашого курсу. Наша платформа, створена спільнотою, допомагає студентам досягати успіху!
6. Why are 2 misses observed during the first execution and 2 hits during the second execution in the second table? (1.5 pt)
5. What do the observations recorded in the first table indicate for the "2-way" and "4-way" configurations? (1.5 pt)
Activity 2: Understanding the Limits of Direct-Mapped Cache Organization
Flush the cache memory by clicking the "FLUSH" button.
Insert the following instructions after the last LDB instruction in the program from Activity 1:
LDB 17, R00
LDB 33, R00
Execute the following instructions individually, one by one:
LDB 0, R00
LDB 17, R00
LDB 33, R00
4. What is the main cause of the high number of cache misses in this activity? (3 pts)
Activity 2: Understanding the Limits of Direct-Mapped Cache Organization
1. Flush the cache memory by clicking the "FLUSH" button.
Insert the following instructions after the last LDB instruction in the program from Activity 1:
LDB 17, R00
LDB 33, R00
2. Then, execute the following instructions individually, one by one:
LDB 0, R00
LDB 17, R00
LDB 33, R00
3. Repeat the individual execution of these instructions and identify the addresses, data, and blocks that result in cache misses. (1.5 points)
Activity 1: Understanding Direct-Mapped Cache Organization
1. Open the CPU-OS Simulator. Create a new program and enter the following code instruction by instruction (click on the "Instructions" tab, then click "ADD NEW", and select "NEW INSTRUCTION" for each instruction).
This program writes the numbers from 0 to 63 into memory addresses 0 to 63.
MOV #0, R01
STB R01, @R01
CMP #63, R01
JEQ 31
ADD #1, R01
JMP 6
HLT
2. Run the program by clicking "RUN", and observe the contents of the data memory by selecting "SHOW PROGRAM DATA MEMORY".
Then click "SHOW CACHE" to open the cache memory window.Check the "STAY ON TOP" option and click "FLUSH".
3. Cache Configuration
Configure the cache memory with the following parameters:
Block Size: 4
Cache Type: Direct Mapped
Cache Size: 16
Write Policy: Write-Back
4. Additional Instructions
Insert the following instructions after the instruction JMP 6:
LDB 0, R00
LDB 2, R00
LDB 4, R00
LDB 6, R00
LDB 8, R00
5. Execute the LDB instructions one by one by double-clicking each line.
8. What explains the number of reported cache hits? (1.5 pt)
Activity 1: Understanding Direct-Mapped Cache Organization
1. Open the CPU-OS Simulator. Create a new program and enter the following code instruction by instruction (click on the "Instructions" tab, then click "ADD NEW", and select "NEW INSTRUCTION" for each instruction).
This program writes the numbers from 0 to 63 into memory addresses 0 to 63.
MOV #0, R01
STB R01, @R01
CMP #63, R01
JEQ 31
ADD #1, R01
JMP 6
HLT
2. Run the program by clicking "RUN", and observe the contents of the data memory by selecting "SHOW PROGRAM DATA MEMORY".
Then click "SHOW CACHE" to open the cache memory window.Check the "STAY ON TOP" option and click "FLUSH".
3. Cache Configuration
Configure the cache memory with the following parameters:
Block Size: 4
Cache Type: Direct Mapped
Cache Size: 16
Write Policy: Write-Back
4. Additional Instructions
Insert the following instructions after the instruction JMP 6:
LDB 0, R00
LDB 2, R00
LDB 4, R00
LDB 6, R00
LDB 8, R00
5. Execute the LDB instructions one by one by double-clicking each line.
7. What causes the number of cache misses reported? (0.75 pt)
Activity 1: Understanding Direct-Mapped Cache Organization
1. Open the CPU-OS Simulator. Create a new program and enter the following code instruction by instruction (click on the "Instructions" tab, then click "ADD NEW", and select "NEW INSTRUCTION" for each instruction).
This program writes the numbers from 0 to 63 into memory addresses 0 to 63.
MOV #0, R01
STB R01, @R01
CMP #63, R01
JEQ 31
ADD #1, R01
JMP 6
HLT
2. Run the program by clicking "RUN", and observe the contents of the data memory by selecting "SHOW PROGRAM DATA MEMORY".
Then click "SHOW CACHE" to open the cache memory window.Check the "STAY ON TOP" option and click "FLUSH".
3. Cache Configuration
Configure the cache memory with the following parameters:
Block Size: 4
Cache Type: Direct Mapped
Cache Size: 16
Write Policy: Write-Back
4. Additional Instructions
Insert the following instructions after the instruction JMP 6:
LDB 0, R00
LDB 2, R00
LDB 4, R00
LDB 6, R00
LDB 8, R00
5. Execute the LDB instructions one by one by double-clicking each line.
6. What do the LDB instructions represent? (0.75 pt)
Activity 1: Understanding Direct-Mapped Cache Organization
1. Open the CPU-OS Simulator. Create a new program and enter the following code instruction by instruction (click on the "Instructions" tab, then click "ADD NEW", and select "NEW INSTRUCTION" for each instruction).
This program writes the numbers from 0 to 63 into memory addresses 0 to 63.
MOV #0, R01
STB R01, @R01
CMP #63, R01
JEQ 31
ADD #1, R01
JMP 6
HLT
2. Run the program by clicking "RUN", and observe the contents of the data memory by selecting "SHOW PROGRAM DATA MEMORY".
Then click "SHOW CACHE" to open the cache memory window. Check the
3. Cache Configuration
Configure the cache memory with the following parameters:
Block Size: 4
Cache Type: Direct Mapped
Cache Size: 16
Write Policy: Write-Back
4. Additional Instructions
Insert the following instructions after the instruction JMP 6:
LDB 0, R00
LDB 2, R00
LDB 4, R00
LDB 6, R00
LDB 8, R00
5. Execute the LDB instructions one by one by double-clicking each line.
Based on the values observed in the cache memory, identify which addresses and data result in a cache hit. (1.5 points)?