The diagram below depicts a conventional digital counter functioning as a frequency meter. The oscillator frequency is . The decade dividers allow division of the oscillator frequency by sucessive multiples of 10, from 1 to , to establish the time base frequency ().

Assuming all the remaining components are ideal, calculate the minimum relative error (in parts per million, ppm) for the measurement of an input signal frequency of .

The conventional digital counter with the simplified diagram representation shown below is operating as a frequency meter. The oscilator frequency is and the decade divider provides the time-base selection of frequency signals , .

Assuming an input signal with frequency , what is the number of pulses obtained by the decade counter when the most adequate time base has been chosen?

Consider the following digital-to-analog converter (DAC), which uses a 3-bit digital word () as the input to control the switches shown in the figure— is the least significant bit (LSB) and is most significant bit (MSB).

For example, for any , if ’1’ the respective switches are closed, implying that the switches controlled by ’0’ are open.

Assuming and the reference voltage , what is the analog output voltage for a binary input of ?

Consider the following digital-to-analog converter (DAC), which uses a 3-bit word () to control which of the switches turns on (’1’ means closed) while all the others are kept turned off (’0’ means opened). For this end, it uses a decoder that converts each input to a 8-bit word () by means of one-hot encoding (only a single bit is ’1’).

Assuming the reference voltage , what is the analog output voltage for a binary input 101.

Consider the dual-slope integrating analog-to-digital converter (ADC) shown in figure, with a full-scale counting taking for a sampled-imput

Find the total conversion time.

Consider the -bit successive-approximation register (SAR) analog-to-digital converter (ADC) with full-scale voltage and internal clock frequency (SAR logic) of , faster than the sampling frequency (). Each comparison takes clock cycles.

Find the conversion time for an input voltage of .

Consider the -bit successive-approximation register (SAR) analog-to-digital converter (ADC) shown in the figure.

Determine the SAR value at the cycle when the input is and .

Consider the subranging -bit half-flash ADC shown in the figure (the ADCs employ uniform mid-rise quantizers). All the components are ideal, including rail-to-rail inputs/outputs with . The only exception is in the DAC output offset, which due to a fabrication error is .

For a sampled input voltage of , determine the digital output in binary.

In the following analog-to-digital converter (ADC), employing a half-flash architecture, consider , , and uniform mid-rise quantizers in the flash ADCs.

Obtain the analog voltage at the output of the residue amplifier, indicated as in the figure.

Consider the subranging -bit half-flash ADC shown in the figure (the ADCs employ uniform mid-rise quantizers). All the components are ideal, including rail-to-rail inputs/outputs with . The only exception is in the DAC output offset, which due to a fabrication error is .

For a sampled input voltage of , determine the digital output in binary.