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This type of hazard may occur when the latter instruction (j) stores the result of its execution in the resource (register or memory location) that earlier instruction (i) uses as their argument. The problem appears when the execution of earlier instruction (i) is delayed, and the latter instruction (j) is finished before earlier instruction (i) can take its argument. It may lead to a wrong result of the execution instruction (i). The typical way to remove such a dependency is to delay the completion of the execution instruction (j) until the execution of instruction (i) is completed. To illustrate this problem, the following code will be used:
;WinMIPS64 WAR hazard example .dataA: .double 10.0B: .double 5.0C: .double 3.5D: .double 1.0E: .double 3.14.0res: .double 0.0 .textmain: LDC1 f2,A(r0) LDC1 f3,B(r0) LDC1 f4,C(r0) LDC1 f5,D(r0) LDC1 f6,E(r0) add.d f2,f2,f3 sub.d f2,f2,f4 mul.d f4,f5,f6 SDC1 f2,res(r0) syscall 0
Enable data forwarding mechanism and execute the example program. Analyze the clock cycle diagram and find the instruction that causes WAR stall.
Mark the instruction that causes WAR stall.