Consider a processor that generate the virtual address 0x00320F28 in the IF stage of a pipeline processor. Assuming that the corresponding instruction is in the cache memory (we have a cache hit), calculate the time (in number of cycles) required for performing the translation

from virtual  (VA) to physical (PA) address of the previous address, asuming that a hit on the TLB requires 0.25 cycles and a miss requires 27 clock cycles (TLB access is performed in parallel with page table access). Assume that we have pages of 4KB and the

state of the TLB and page table are:

Page Table           TLB

1 452 3A           

VA= Virtual Adress, PA= Physical Address, V= Valid bit