A processor has a

separate L1 I-cache and L1 D-cache that share the same L2 cache. Both L1 caches

have a hit latency of 1 cycle(s). The I-cache has a miss rate of 2% and the D-cache has a miss rate of 11%. The L2 cache has a hit latency of 18 cycles and a miss rate of 6%. L2 misses are serviced

by DRAM which has an average memory access time of 163 cycles.

What is the average

memory access time of the L1 I-cache? Round your answer to 2 decimal places.