R-A-W hazard

R-A-W hazard is one of the most common problems related to the pipelined and parallel instruction execution by the processor. This type of hazard occurs when the later instruction (j) requires  the results of the previous instruction (i) to be executed, but the execution of the earlier instruction (i) has not finished yet (the completion of the execution – the end of the WB phase of the instruction cycle in MIPS). If the program execution is not interfered with, it may happen that the later instruction (j) will perform operations on an incorrect argument - the correct value of the argument  for the instruction (j) is not available before the execution of the earlier instruction (i) is completed. The occurrence of this type of disturbance can be observed during the execution of the example program:

;MIPS64 RAW hazard example

Analyze that program and calculate how many clock cycles are needed to execute it on the sequential processor. Let’s assume that the execution of any instruction takes 5 clock cycles.

How many clock cycles are needed to execute this program on a sequential processor?