In a system that uses instruction pipelining, if the probability of a control hazard (branch misprediction) is 20% and the penalty for each misprediction is 3 cycles, what is the effective CPI if the ideal CPI is 1.2?

A processor has a cache hit rate of 90% and a memory access time of 100 cycles. If the cache access time is 5 cycles, what is the effective memory access time (EMAT)?

 If a system has an instruction mix with 40% arithmetic, 30% load/store, and 30% branch instructions, and each takes 2, 3, and 4 cycles respectively, what is the average CPI?

A CPU fetches an instruction in 2 cycles, decodes it in 1 cycle, and executes it in 3 cycles. If the system has a pipeline, what is the ideal speedup for executing 100 instructions, assuming no stalls?

Care dintre rulmentii prezentati in figurile de mai jos:

c au inelul interior / exterior realizat din doua bucati

d au inelul interior / exterior detasabil

In corespondenta cu numarul afisat in stanga fiecarei figuri precizati:

a. denumirea tipului de rulment prezentat in figura

b. tipul sarcinilor preluate

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2

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A processor follows the Fetch-Decode-Execute cycle. If an instruction takes 5 cycles on average and the processor operates at 2 GHz, how many instructions can it execute per second?

A computer system has a pipelined execution model where the probability of a stall due to a data hazard is 15%, and the average stall penalty is 2 cycles. If the ideal CPI is 1, what is the actual CPI considering data hazards?

Consider a superscalar processor capable of issuing 4 instructions per cycle. If a program has 1000 instructions and executes with an average Instruction-Level Parallelism (ILP) of 2.5, how many cycles will it take to complete execution (ignoring stalls and dependencies)?

A processor has a cache hit rate of 80% and a cache access time of 2 cycles. If the main memory access time is 50 cycles, what is the average memory access time (AMAT)?