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Computer and Сomputer System Architecture (UWE – E.Merchan)
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Consider an instruction format where some opcodes require an additional operand byte (immediate or address). Which action is a direct consequence of correct instruction decoding?
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SP is initialized to 2FH. An LCALL instruction at address 0120H is executed, and the next instruction after LCALL is at 0123H. Which statement is correct about what is pushed to the stack?
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What condition triggers an external interrupt when configured for edge-triggered mode?
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The SP is initiated at 40H. The code executes: LCALL SUB ; (next instruction). No other pushes occur. Immediately after LCALL finishes, which internal RAM locations contain the return address bytes?
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When register bank 2 is selected, what internal RAM addresses correspond to registers R0-R7?
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Which Control Unit component generates the ordered control signals required to execute an LCALL instruction?
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A computer stores both instructions and data in the same main memory and fetches them over the same bus. Which consequence most directly follows from this design?
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Which characteristic is most fundamental to RISC (Reduced Instruction Set Computer) architecture philosophy?
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In a microprogrammed CPU datapath, an ALU operation cannot begin until operands are available at the ALU inputs. Which statement best captures this dependency?
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How are different memory spaces distinguished when examining memory contents during debugging?
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