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UEF 1.2.1:Architectures évoluées des ordinateurs

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4. What observations can be made about the correlation between the miss rate and the cache size and type? (4 pts)

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6. Why are 2 misses observed during the first execution and 2 hits during the second execution in the second table? (1.5 pt)

d. The first access to addresses 0 and 17 caused cache misses due to a cold cache. During the second execution, these addresses were already present in the cache, resulting in cache hits.

100%

b. Cache misses occur due to an error in the assignment of blocks within the cache.

c. The cache was emptied after each execution, which caused the accesses to result in misses.

Cache misses occurred during the first execution because the data were not properly loaded into the cache memory.

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5. What do the observations recorded in the first table indicate for the "2-way" and "4-way" configurations? (1.5 pt)

The 2-way configuration results in more cache hits than the 4-way configuration because it has a greater number of sets, reducing conflicts for these specific addresses.

The 4-way configuration results in more cache misses because each set is larger, which can increase conflicts for certain memory accesses.

c. In the 2-way configuration, each address is mapped to a specific set, while in the 4-way configuration, each address can be placed in any block within the set, allowing greater flexibility.

b. In the 4-way configuration, all addresses (0,4,8, and 13) are mapped to set 0.

100%

d. For the 2-way configuration, addresses 0 and 8 belong to set 0, and addresses 4 and 13 belong to set 1.

100%

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Activity 2: Understanding the Limits of Direct-Mapped Cache Organization

Flush the cache memory by clicking the "FLUSH" button.

Insert the following instructions after the last LDB instruction in the program from Activity 1:

LDB 17, R00

LDB 33, R00

Execute the following instructions individually, one by one:

LDB 0, R00

LDB 17, R00

LDB 33, R00

4. What is the main cause of the high number of cache misses in this activity? (3 pts)

The cache is too small and cannot store the required data.

The data read are not written correctly into the cache memory.

d. The processor cannot access the data in memory.

The high number of cache misses is mainly caused by conflict misses in the direct-mapped cache. In a direct-mapped cache, each memory block can be placed in only one specific cache line. The addresses 0, 17, and 33 map to the same cache line. As a result, each new access replaces the previous block stored in that line. This repeated replacement causes frequent cache misses, even when the same addresses are accessed repeatedly.

100%

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Activity 2: Understanding the Limits of Direct-Mapped Cache Organization

1. Flush the cache memory by clicking the "FLUSH" button.

Insert the following instructions after the last LDB instruction in the program from Activity 1:

LDB 17, R00

LDB 33, R00

2. Then, execute the following instructions individually, one by one:

LDB 0, R00

LDB 17, R00

LDB 33, R00

3. Repeat the individual execution of these instructions and identify the addresses, data, and blocks that result in cache misses. (1.5 points)

Addr=0035

Data=23

Blocks=0

Addr=0033

Data=21

Blocks=0

Addr=0032

Data=20

Blocks=0

100%

Addr=0034

Data=22

Blocks=0

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Activity 1: Understanding Direct-Mapped Cache Organization

1. Open the CPU-OS Simulator. Create a new program and enter the following code instruction by instruction (click on the "Instructions" tab, then click "ADD NEW", and select "NEW INSTRUCTION" for each instruction).

This program writes the numbers from 0 to 63 into memory addresses 0 to 63.

MOV #0, R01

STB R01, @R01

CMP #63, R01

JEQ 31

ADD #1, R01

JMP 6

HLT

2. Run the program by clicking "RUN", and observe the contents of the data memory by selecting "SHOW PROGRAM DATA MEMORY".

Then click "SHOW CACHE" to open the cache memory window.

Check the "STAY ON TOP" option and click "FLUSH".

3. Cache Configuration

Configure the cache memory with the following parameters:

Block Size: 4

Cache Type: Direct Mapped

Cache Size: 16

Write Policy: Write-Back

4. Additional Instructions

Insert the following instructions after the instruction JMP 6:

LDB 0, R00

LDB 2, R00

LDB 4, R00

LDB 6, R00

LDB 8, R00

5. Execute the LDB instructions one by one by double-clicking each line.

8. What explains the number of reported cache hits? (1.5 pt)

The cache hits are due to random cache management.

After each miss, a block of four data items is loaded into the cache memory, which allows subsequent accesses to result in cache hits.

100%

Each data item is always loaded individually into the cache.

The cache is completely filled after the first access, which explains the cache hits.

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Activity 1: Understanding Direct-Mapped Cache Organization

This program writes the numbers from 0 to 63 into memory addresses 0 to 63.

MOV #0, R01

STB R01, @R01

CMP #63, R01

JEQ 31

ADD #1, R01

JMP 6

HLT

2. Run the program by clicking "RUN", and observe the contents of the data memory by selecting "SHOW PROGRAM DATA MEMORY".

Then click "SHOW CACHE" to open the cache memory window.

Check the "STAY ON TOP" option and click "FLUSH".

3. Cache Configuration

Configure the cache memory with the following parameters:

Block Size: 4

Cache Type: Direct Mapped

Cache Size: 16

Write Policy: Write-Back

4. Additional Instructions

Insert the following instructions after the instruction JMP 6:

LDB 0, R00

LDB 2, R00

LDB 4, R00

LDB 6, R00

LDB 8, R00

5. Execute the LDB instructions one by one by double-clicking each line.

7. What causes the number of cache misses reported? (0.75 pt)

b. Cold cache (cache memory is empty)

100%

d. Caused by an overload of the memory bus.

a. Because of poor management of the main memory.

c. Caused by a processor hardware problem.

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Activity 1: Understanding Direct-Mapped Cache Organization

This program writes the numbers from 0 to 63 into memory addresses 0 to 63.

MOV #0, R01

STB R01, @R01

CMP #63, R01

JEQ 31

ADD #1, R01

JMP 6

HLT

2. Run the program by clicking "RUN", and observe the contents of the data memory by selecting "SHOW PROGRAM DATA MEMORY".

Then click "SHOW CACHE" to open the cache memory window.

Check the "STAY ON TOP" option and click "FLUSH".

3. Cache Configuration

Configure the cache memory with the following parameters:

Block Size: 4

Cache Type: Direct Mapped

Cache Size: 16

Write Policy: Write-Back

4. Additional Instructions

Insert the following instructions after the instruction JMP 6:

LDB 0, R00

LDB 2, R00

LDB 4, R00

LDB 6, R00

LDB 8, R00

5. Execute the LDB instructions one by one by double-clicking each line.

6. What do the LDB instructions represent? (0.75 pt)

They are memory access instructions for reading.

100%

They are multiplication instructions.

They are conditional jump instructions.

They are memory write instructions.

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Activity 1: Understanding Direct-Mapped Cache Organization

This program writes the numbers from 0 to 63 into memory addresses 0 to 63.

MOV #0, R01

STB R01, @R01

CMP #63, R01

JEQ 31

ADD #1, R01

JMP 6

HLT

2. Run the program by clicking "RUN", and observe the contents of the data memory by selecting "SHOW PROGRAM DATA MEMORY".

Then click "SHOW CACHE" to open the cache memory window.

Check the

"STAY ON TOP" option and click "FLUSH".

3. Cache Configuration

Configure the cache memory with the following parameters:

Block Size: 4

Cache Type: Direct Mapped

Cache Size: 16

Write Policy: Write-Back

4. Additional Instructions

Insert the following instructions after the instruction JMP 6:

LDB 0, R00

LDB 2, R00

LDB 4, R00

LDB 6, R00

LDB 8, R00

5. Execute the LDB instructions one by one by double-clicking each line.

Based on the values observed in the cache memory, identify which addresses and data result in a cache hit. (1.5 points)?

Addr=0004

Data=04

Blocks=1

Addr=0008

Data=08

Blocks=2

Addr=0002

Data=02

Blocks=0

100%

Addr=0000

Data=00

Blocks=0

Addr=0006

Data=06

Blocks=1

100%

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