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Course 14047
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Cache memory is generally
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A memory circuit stores 32 × 4 = 128 bits. How many external connections are required?
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Cache access time is 20 ns and main memory access time is 100 ns. If hit ratio is 0.8, the average access time is
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In an interleaved memory system, address transfer time = 3 ns, first word access time = 5 ns, next word access time = 4 ns, and data transfer time = 1 ns. For a 4-word block, the block transfer time is
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Cache memory is placed between
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Consider a main memory of size 32K words and cache size 2K words. Block size is 8 words. The cache uses 4-way set associative mapping. Number of bits required for the TAG field is
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Consider a main memory of size 64K words and block size 32 words. Number of bits required for WORD field is
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Consider a main memory of size 32K words and cache size 1K words. Block size is 8 words. Number of bits required for TAG field in direct mapping is
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Cache coherence problem mainly occurs in
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Incoherent data occurs when
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