Crowdly

Add to Chrome

Universities
learn.saylor.org
CS301: Computer Architecture

CS301: Computer Architecture

Looking for CS301: Computer Architecture test answers and solutions? Browse our comprehensive collection of verified answers for CS301: Computer Architecture at learn.saylor.org.

Get instant access to accurate answers and detailed explanations for your course questions. Our community-driven platform helps students succeed!

What is the final step in the fetch cycle of a MIPS processor?

Fetching the instruction from the instruction memory

100%

Executing the operation using the ALU

Decoding the instruction

Reading the program counter value

View this question

Which of the following can be the value of the program counter after fetching of an instruction in a MIPS processor?

Which of the following most accurately describes the execution of a R-type instruction?

Instruction memory and data memory take part

Instruction memory, ALU, and register take part

100%

Data memory and Register File take part

Instruction memory, Register File, ALU, and data memory take part

View this question

If you build a full adder from two half adders, how many gates do you need?

100%

View this question

Which of the following snippets of pseudocode can you use to multiply using a 4 bit hardware adder/subtractor?

Loop a times {
   b = b + b
} answer = b

c = 0
Loop a times {
   c = c + b
} answer = b

100%

Assume b > a
Loop n times {
   b = b - a
   if (b = 0) answer = n
   if(b < 0) answer = n - 1
}

Assume b > a
Loop n times {
   b = b - a
   if (b = 0) answer = 0
   if(b < 0) answer = b + a
}

View this question

Which two gates are used to build a half adder?

What circuitry, in addition to an adder, do you need to perform subtraction in hardware?

NOT gates and MUXes

100%

XNOR gates and DECODERs

OR gates and DEMUXes

AND gates and MUXes

View this question

If you want to design a finite state machine that recognizes the pattern 0101, what is the number of outgoing transitions from each state?

100%

View this question

For this state machine, if we encode states S0 and S1 using a single bit, where 0 represents S0 and 1 represents S1, and we represent the inputs by a and b, then which of the following logic equations will be the state machine's output?

Image failed to load

[a'b + a'b'] S' + [ab + ab'] S

[ab + a'b'] S' + [a'b + ab'] S

[ab + a'b] S' + [a'b' + ab'] S

[ab' + a'b] S' + [ a'b' + ab] S

100%

View this question

Which of the following is true for a 4-bit ripple carry adder?

There is a clock line going to each full adder

There are three stages

Extra gates are needed besides the full adder gates

The adder is slower than a carry look ahead adder