Assuming that a page

table entry stores a physical page number, valid bit, dirty bit, and reference

bit, and that its size in bytes must be a power of 2, how large is the page

table in KiB?

What is the size of

the virtual page number?

What is the size of

the physical page number?

What is the size of

the page offset?

A processor has a

separate L1 I-cache and L1 D-cache that share the same L2 cache. Both L1 caches

have a hit latency of 1 cycle(s). The I-cache has a miss rate of 2% and the D-cache has a miss rate of 11%. The L2 cache has a hit latency of 18 cycles and a miss rate of 6%. L2 misses are serviced

by DRAM which has an average memory access time of 163 cycles.

What is the average

memory access time of the L1 I-cache? Round your answer to 2 decimal places.

A processor has a

separate L1 I-cache and L1 D-cache that share the same L2 cache. Both L1 caches

have a hit latency of 1 cycle(s). The I-cache has a miss rate of 2% and the D-cache has a miss rate of 11%. The L2 cache has a hit latency of 18 cycles and a miss rate of 6%. L2 misses are serviced

by DRAM which has an average memory access time of 163 cycles.

What is the average

memory access time of the L1 D-cache? Round your answer to 2 decimal places.

A processor with 27-bit memory addresses has a 64 KiB 8-way set associative write-through cache with a block size of 32 bytes.

What is the total number

of bits needed to construct the cache?

A processor with 27-bit memory addresses has a 64 KiB 8-way set associative write-through cache with a block size of 32 bytes.

What is the

efficiency of the cache? Report your answer as

a real number (not a percentage) rounded to 2 decimal places.

A processor has a

separate L1 I-cache and L1 D-cache that share the same L2 cache. Both L1 caches

have a hit latency of 1 cycle(s). The I-cache has a miss rate of 2% and the D-cache has a miss rate of 11%. The L2 cache has a hit latency of 18 cycles and a miss rate of 6%. L2 misses are serviced

by DRAM which has an average memory access time of 163 cycles.

If the processor’s base

CPI is 2 when an

ideal memory is assumed, what is the actual CPI of the processor when memory

stalls are considered for a program that has a 18% fraction of memory access instructions? Round your answer to

2 decimal places.

A processor has a

separate L1 I-cache and L1 D-cache that share the same L2 cache. Both L1 caches

have a hit latency of 1 cycle(s). The I-cache has a miss rate of 2% and the D-cache has a miss rate of 11%. The L2 cache has a hit latency of 18 cycles and a miss rate of 6%. L2 misses are serviced

by DRAM which has an average memory access time of 163 cycles.

What is the average

memory access time of the L2 cache? Round your answer to 2 decimal places.