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Course 31452

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A processor with 27-bit memory addresses has a 64 KiB 8-way set associative write-through cache with a block size of 32 bytes.

How many sets does

the cache have?

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A processor with 25-bit memory addresses has a 128 KiB direct-mapped write-back cache with a block size of 64 bytes.

How many blocks does the cache have?

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A processor with 27-bit memory addresses has a 64 KiB 8-way set associative write-through cache with a block size of 32 bytes.

How many bits is the

tag?

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A processor with 25-bit memory addresses has a 128 KiB direct-mapped write-back cache with a block size of 64 bytes.

What is the efficiency of the cache? Report your answer as

a real number (not a percentage) rounded to 2 decimal places.

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A processor with 25-bit memory addresses has a 128 KiB direct-mapped write-back cache with a block size of 64 bytes.

What is the total number of bits needed to construct the cache?

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A processor with 25-bit memory addresses has a 128 KiB direct-mapped write-back cache with a block size of 64 bytes.

How many bits is the tag?

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Write the following C function in MIPS assembly language:

int foo(int x, int* a) {

int i; // Place i in $s0

if(x == 13) {

i = x | 10;

} else {

i = x - 2;

do {

i = a[i];

} while(i < 5);

a[4] = x & i;

}

return i/32;

}

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Write the following C function in MIPS assembly language:

int foo(int N, int* a) {

int i; // Place i in $s0

int x = N; // Place x in $s1

for(i = 256; i != 0; i /= 4) {

x = bar(i & x, a[i]) - 13;

if(N > x) {

a[i] = x;

}

}

return x;

}

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