if a result of a recent operation could be interpreted as a negative number

the currently executed instruction operation code

if a result of addition operation was negative

if if the recent operation result was 0

was commonly used in the past to implement main interconnections in computer systems

is currently used to implement the highest speed interconnections in modern computer systems

is rarely used to implement high-speed interconnections in favor of serial physical connections

moves towards lower memory addresses with each stack push operation

moves towards lower memory addresses with each stack pop operation

points to the recently pushed item on the stack

There are multiple Program Counter (or Instruction Pointer) registers.

The number of virtual CPUs is equal to the number of the pipeline stages

At a given point in time, the CPU may process parts of multiple instructions

The CPU is visible in the system as multiple CPUs

Program instructions are divided into smaller steps

allows for running multiple applications at the same time

may look like multiple CPUs which share common cache and main memory

allows for running only one application at the same time

Stores large amounts of data

Is a part of a CPU

Is the core component responsible for calculations

Contains a block called CPU

Controls program execution

in some degree may compensate the overhead needed to start the data transfer

is usually faster than random accesses

is in most cases equally efficient as random accesses

may use two separate memory blocks, e.g. one for executable code, and one for data

usually has only one single block of memory to store both code and data

implementation of pipelined instruction execution is in general much more difficult for the Harvard architecture than for the von Neumann architecture

naturally optimized for instruction execution flow in multiple consecutive stages

Because we would like to have a faster access to our storage

Because we would like to avoid losing data in case of a disk failure

Because we may want to have less expensive hardware in our computer system

Because we would like to save energy

Because we would like to store and retrieve data in a sequential manner

Multi-threaded CPU uses much more chip area than the multi-core equivalent.

Multi-threaded CPU performance gain is achieved by utilizing chip area more efficiently than in multi-core implementations.

Multi-threaded CPU uses much less chip area than the multi-core equivalent.

The hardware resources are utilized more efficiently in the multi-threaded CPUs than in regular multi-core implementations.