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CA & OS (Computer Architecture) - EFREI - Fall 2025
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A sequencer, which can be implemented in a control block of a CPU
A pipelined CPU executes a conditional branch instruction for which it could not predict if the branch will be “taken” (i.e. execution moved to the branch target address) or “not taken” (i.e. uninterrupted execution of the program after the conditional branch instruction).
In such a case the pipelined CPU may have to deal with: