Observation of the pipelined execution of a simple program

In this section you will try to evaluate the impact of the pipelined execution of the program on its performance.

Prepare and load the test program (copy & paste following code):

In menu “Configure” check and enable the option “Enable forwarding”.

Execute the program in single cycle instruction mode. Observe the pipeline window and the clock cycle diagram.

What is the number of clock cycles (n) used for the execution of  this program that appears in the "Statistic" window.

In this section, you will evaluate how long it takes to execute different types of the instructions of the MIPS computer.

Number of clock cycles for dadd instruction (integer addition)

Load and execute in step mode following program:

        .text

As a result of the execution you should receive clock cycle diagram of the execution similar to this on the image:

Analyze this clock cycle diagram of execution of the program and answer the question: 

The user program consists of 25 instructions, each of which is executed

in one clock cycle, and 5 instructions, each of which executes in 5 clock

cycles.

The average cycles per

instruction (

In this section, you will evaluate how long it takes to execute different types of the instructions of the MIPS computer.

Number of clock cycles for dadd instruction (integer addition)

Load and execute in step mode following program:

        .text

As a result of the execution you should receive clock cycle diagram of the execution similar to this on the image:

Analyze this clock cycle diagram of execution of the program and answer the question: 

Control hazard

Control hazards are mainly related to the processor's execution of jump instructions (unconditional or conditional). To observe the behavior of the pipeline during the execution of jump instructions, the following program will be used:

;WinMIPS64 control hazard

Find the part of the clock cycle diagram that shows the first execution of the beqz r9, end_loop instruction. 

Which instruction is fetched next (enters in the IF phase on clock cycle diagram) ?

Which instruction is executed next after beq r9, r0, end_loop (enters in the EX phase on clock cycle diagram) ??

W-A-R hazard

This type of hazard may occur when the latter instruction (j) stores the result of its execution in the resource (register or memory location) that earlier instruction (i) uses as their argument. The problem appears when the execution of earlier instruction (i) is delayed, and the latter instruction (j) is finished before earlier instruction (i) can take its argument. It may lead to a  wrong result of the execution instruction (i). The typical way to remove such a dependency is to delay the completion of the execution instruction (j) until the execution of instruction (i) is completed. 

;WinMIPS64 WAR hazard example

Enable data forwarding mechanism and execute the example program.

Mark the instruction that causes WAR stall.

How many instructions were executed?

R-A-W hazard

R-A-W hazard is one of the most common problems related to the pipelined and parallel instruction execution by the processor. This type of hazard occurs when the later instruction (j) requires  the results of the previous instruction (i) to be executed, but the execution of the earlier instruction (i) has not finished yet (the completion of the execution – the end of the WB phase of the instruction cycle in MIPS). If the program execution is not interfered with, it may happen that the later instruction (j) will perform operations on an incorrect argument - the correct value of the argument  for the instruction (j) is not available before the execution of the earlier instruction (i) is completed. The occurrence of this type of disturbance can be observed during the execution of the example program:

;MIPS64 RAW hazard example

Analyze that program and calculate how many clock cycles are needed to execute it on the sequential processor. Let’s assume that the execution of any instruction takes 5 clock cycles.

How many clock cycles are needed to execute this program on a sequential processor?

Calculate the speedup in relation to the pipelined execution of the program with the DF mechanism disabled.

speedupDF = CPIpip / CPIpipDF

What is the speedup value?