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Consider the following code. It is the only code in the module. always@(po...

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Consider the following code. It is the only code in the module.

always@(posedge clock)

begin A <= C & D; end

always@(*)

E = A+B;

If it is synthesized with the following constraints

Create_clock -period 8 -waveform {0 4} –name clock

set_clock_skew -uncertainty 1.0 clock

set_input_delay 1.0 -clock clock all_inputs() – clock

set_output_delay 2.0 -clock clock all_outputs() – clock

Flip flop tck-Q delay is 1 ns, setup time is 1 ns, and hold time 1 ns, all logic gate delays vary between 1 and 2 ns.

What is the maximum allowed delay for the logic A+B? Give your answer in ns without the units.

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