Activity 1: Understanding Direct-Mapped Cache Organization 1. Open the CPU-OS Simulator. Create a new program and enter the following code instruction by instruction (click on the "Instructions" tab, then click "ADD NEW", and select "NEW INSTRUCTION" for each instruction). This program writes the numbers from 0 to 63 into memory addresses 0 to 63. MOV #0, R01 STB R01, @R01 CMP #63, R01 JEQ 31 ADD #1, R01 JMP 6 HLT 2. Run the program by clicking "RUN" , and observe the contents of the data memory by selecting "SHOW PROGRAM DATA MEMORY" . Then click "SHOW CACHE" to open the cache memory window.
Check the "STAY ON TOP" option and click "FLUSH" . 3. Cache Configuration Configure the cache memory with the following parameters: Block Size: 4 Cache Type: Direct Mapped Cache Size: 16 Write Policy: Write-Back 4. Additional Instructions Insert the following instructions after the instruction JMP 6: LDB 0, R00 LDB 2, R00 LDB 4, R00 LDB 6, R00 LDB 8, R00 5. Execute the LDB instructions one by one by double-clicking each line. 8. What explains the number of reported cache hits? (1.5 pt)

Question

Activity 1: Understanding Direct-Mapped Cache Organization 1.   Open the CPU-OS Simulator. Create a new program and enter the following code instruction by instruction (click on the "Instructions" tab, then click "ADD NEW", and select "NEW INSTRUCTION" for each instruction).   This program writes the numbers from 0 to 63 into memory addresses 0 to 63. MOV #0, R01   STB R01, @R01    CMP #63, R01   JEQ 31    ADD #1, R01   JMP 6    HLT  2. Run the program by clicking  "RUN" , and observe the contents of the data memory by selecting  "SHOW PROGRAM DATA MEMORY" . Then click  "SHOW CACHE"  to open the cache memory window. 
 Check the  "STAY ON TOP"  option and click  "FLUSH" . 3. Cache Configuration Configure the cache memory with the following parameters:  Block Size: 4 Cache Type: Direct Mapped  Cache Size: 16 Write Policy: Write-Back 4. Additional Instructions Insert the following instructions after the instruction JMP 6:  LDB 0, R00   LDB 2, R00   LDB 4, R00   LDB 6, R00   LDB 8, R00   5. Execute the LDB instructions one by one by double-clicking each line. 8. What explains the number of reported cache hits? (1.5 pt)

Answer

d.  
 
 The cache hits are due to random cache management.

Answer

c.  After each miss, a block of four data items is loaded into the cache memory, which allows subsequent accesses to result in cache hits.

Answer

a.  
 Each data item is always loaded individually into the cache.

Answer

b.  The cache is completely filled after the first access, which explains the cache hits.

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Activity 1: Understanding Direct-Mapped Cache Organization 1. Open the CPU-O...

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