What is wrong with the following code fragment. More than one thing might be wrong. You lose answers for an incorrect choice.

Note, this is the entire module - there is no additional code

module fubar1 (input clock, input [1:0] H, input [2:0] B; output wire A);

 integer i;

 always@(B, H)

 begin

 A = 0;

 for (i=0; i<=H; i=i+1)

if (B[i]) A=!A;

end

endmodule