Write an assertion in Verilog 95 that checks that a particular bus CHANGES every clock cycle and does not take the value xx or zz. I.e. changes to and from xx or zz are errors. E.g. The change from xx to 80 is flagged as an error but no error is reported below when 80 changes to 03. E.g. Reports errors as follows. [10 points]

The overall structure is

//synopsys off

‘ifdef Assertions_on

Your code goes here

‘endif

// synopsys on