Add to Chrome
✅ The verified answer to this question is available below. Our community-reviewed solutions help you understand the material better.
The constraints specified in the class synthesis script were:
Clock period, uncertainty; input clock-Q delay; input driver gate and pin; output setup delay; output load gate and pin
Area desired
Clock period, uncertainty; clock period lost to external delays to input pins; input driver gate and pin; clock period lost to external delays from output pins; output load gate and pin
Clock period, uncertainty; Library choice; hold time repair rules
Get Unlimited Answers To Exam Questions - Install Crowdly Extension Now!