Consider the

following code implemented exactly as described.

module (input

clock, start; output reg A, B, C, D);

always@(posedge

clock)

begin

 if (start) {A,B,C,D} = 4'hA;

  else

  begin

     A <= (A & B) | (C & D);

     B <= B ^ C;

     C <= A ^ D;

     D <= A ^ C;

  end

end

Each logic gate

has a delay of (1:2:6) (min:typ:max).