You are designing an engine that modifies packets in a stream. The incoming packets on “In” are 8 bits of content. The packets you will produce on “Out” have 8 bits of content and a 9^th parity bit. You are to use odd parity. Each packet is to appear THREE clock cyles after In changes and with the correct parity. An example is given below. All values are in Hex.

The module header is given below.

module exam (input clock, input [7:0] In, output reg [8:0] out);

write the rest of the module. This question is worth double the normal question at 10 points. Declare all variables. Make sure the module is complete and syntactically correct.