You have access to a C level model of the chip and your module is clearly identifiable in that C level model. How might you use this model to obtain test vectors and expected outputs for your model. Select all reasonable (i.e. valid) answers.

Question

You have access to a C level model of the chip and your module is clearly identifiable in that C level model.  How might you use this model to obtain test vectors and expected outputs for your model.  Select all reasonable (i.e. valid) answers.

Accepted Answer

Obtain vectors from chip level runs with random inputs.

Accepted Answer

Obtain vectors from chip level runs of actual code and examples.

Answer

Use PLI to replace the C description of your module with a Verilog description

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You have access to a C level model of the chip and your module is clearly identi...

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