Consider the following code implemented exactly as described.

always@(posedge clock)

   begin

    A <= B;

    B <= F;

    E <= H;

  end

assign C = A ^ B;

assign F = C | E;

assign H = F | A;

Each gate has a delay from its input to output as given as {1 : 2 : 3}, t_Cp_Q is {3 : 4 : 5} the clock skew is 1 ns, the flip-flop setup time is 1 ns and the hold time 2 ns.  Format above is {min : typical : max}.

Is there potential for a hold violation in this logic?