Both of these questions apply to the following code implemented exactly as described.

module A1 (input clock, E, F; output reg A, B);

wire C

always@(posedge clock)

   begin

    A <= C;

    B <= F;

   end

assign C = E | F;

endmodule

Each gate has a delay from its input to output as given as {1 : 2 : 3}, t_Cp_Q is {2 : 3 : 5} the clock skew is 1 ns, the flip-flop setup time is 1 ns and the hold time 1 ns.  Format above is {min : typical : max}. 

This module is part of a hierarchy 

     A1 U1 (clock, E, F, A, B);

     A2 U2 (clock, G, H, E, F);

A2 is another module with a clock two inputs and two outputs.  If you were synthesizing A2 by itself, (i.e. A1 is not being synthesized in the same run) what vales should be assigned for  the  output delay for the ports of module A2.  Ignore any interconnect delay.

 Give your answers as integers

 Output delay