What is wrong with the following code fragment?
always@(posedge clock)
begin
D

Question

What is wrong with the following code fragment? 
 always@(posedge clock) 
    begin 
     D <= A & G; 
     if (E) G <= D | F; 
    end

Accepted Answer

Nothing is wrong with this code fragment.

Answer

E is missing from the second sensitivity list

Answer

D should not be assigned like this.  Unbuildable “wired-or” logic is implied.

Answer

A timing loop (or arc) is present.

Answer

Unintentional latches are being built.

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